1. Field of the Invention
The invention generally relates to integrated circuit components and, in particular, to two-input multiplexers.
2. Description of Related Art
Two-input multiplexers are in common use in a wide variety of integrated circuits. A simple two-input multiplexer 10 is illustrated in FIG. 1. Multiplexer 10 of FIG. 1 receives a pair of input signals d0 and d1 along input lines 12 and 14 respectively. Multiplexer 10 also receives an input select signal along a select line 16 which designates either the d0 input or the d1 input. Multiplexer 10 operates to transmit a single output signal which corresponds to either the d0 signal or the d1 signal depending upon the value of the select signal. To this end, multiplexer 10 includes a pair of NMOS transistors, 18 and 20, and a pair of inverters 22 and 24. A gate of NMOS transistor 18 is connected to select line 16. A gate of NMOS transistor 20 is connected through inverter 22 to select line 16. NMOS transistor 18 has an input connected to input line 12 whereas NMOS transistor 20 has an input connected to input line 14. With this configuration, either transistor 18 or transistor 20, but not both, pass the input signal. The resulting signal is inverted by inverter 24 and output along an output line 26.
Transistors 18 and 20 are herein referred to as pass-gates. As can be seen from FIG. 1, pass-gates 18 and 20 are "equal", i.e., pass-gates 18 and 20 are both NMOS transistors. Because equal pass-gates are employed, the select signal must be inverted prior to transmission to one of the two NMOS transistors. Hence, inverter 22 is required. Although multiplexer 10 is effective for selecting between the two input signals d0 and d1, the need to provide an inverter results in an additional delay before the output signal can be provided. Hence, the multiplexer configuration of FIG. 1 is not ideal for applications requiring high speed switching wherein the additional delay caused by the requirement that the select signal be inverted is undesirable.
FIG. 2 illustrates a somewhat more sophisticated multiplexer 30. Multiplexer 30 of FIG. 2 is referred to as a complementary multiplexer with each of a pair of pass-gates including both a PMOS and an NMOS transistor. Input signals d0 and d1 are received along input lines 32 and 34 respectively. A select input signal is received along line 36. A first pass-gate 38 and a second pass-gate 40 are connected to input lines 32 and 34 respectively. Pass-gate 38 includes an NMOS transistor 39 and a PMOS transistor 41. A gate of NMOS transistor 39 is connected to select line 36. A gate of PMOS transistor 41 is connected through an inverter 42 to select line 36. Second pass-gate 40 likewise includes a PMOS transistor and an NMOS transistor denoted 43 and 45 respectively. However, for pass-gate 40, a gate of PMOS transistor 43 is connected directly to input select line 36 with the gate of NMOS transistor 45 connected through inverter 42 to select line 36. Hence, the configuration of pass-gate 40 is reversed from that of pass-gate 48. Output signals from the pair of pass-gates are connected through an output inverter 44 for transmission along an output line 46.
The complementary multiplexer of FIG. 2 has advantages over the simple multiplexer of FIG. 1, particularly as far as providing a buffered, stable output. However, as with the simple multiplexer of FIG. 1, the complementary multiplexer of FIG. 2 requires that the input select signal be inverted. The necessity of inverting the input select signal causes an additional time delay which is undesirable for high-speed circuitry.